A Selection of Books and Journal Articles Authored by Prof C. L. Liu


Books (titles with * are now on display in the Library Lobby)

* Introduction to Combinatorial Mathematics, McGraw-Hill Book Company, 1968.

* Linear Systems Analysis, with J. W. S. Liu, McGraw-Hill Book Company, 1975.

* Elements of Discrete Mathematics, McGraw-Hill Book Company, 1977.

* Elements of Discrete Mathematics (Chinese translation) 離散數學基礎 / 劉振宏譯. 北京 : 人民郵電出版社 , 1982.

* Pascal, with G. G. Belford, McGraw-Hill Book Company, 1984.

* Elements of Discrete Mathematics, second edition, McGraw-Hill Book Company, 1985.

* Elements of Discrete Mathematics (Chinese translation) 離散數學初步 / 林福來譯. 台北市 : 九章出版社, 1992

* Simulated Annealing for VLSI design, with D. F. Wong, and H. W. Leong, Kluwer Academic Publishers, 1988.

* 愛上層樓,天下遠見出版公司、國立清華大學出版社出版,2002

Journal Articles (titles with * are now on display in the Library Lobby)

"Some Algebraic Properties of Multi-Threshold Functions," IEEE Transactions on Electronic Computers, pp. 935-938, December, 1966.

"Lattice Functions, Pair Algebras, and Finite State Machines," Journal of the Association for Computing Machinery, pp. 442-454, July, 1969.

* "Construction of Sorting Plans," Proceedings of the International Symposium on the Theory of Machines and Computations, pp. 87-98, August, 1971.

"Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment," with J. W. Layland,  Journal of the Association for Computing Machinery, vol. 20, no. 1, pp. 46-61, January, 1973.

* "On a Real-Time Scheduling Problem," with S. K. Dhall, Operations Research, vol. 26, no. 1, pp. 127-140, February, 1978.

"Performance Analysis of Multiprocessor Systems Containing Functional Dedicated Processors," with J. W. S. Liu, Acta Informatica, vol. 10, pp. 95-104, 1978.

* "Combinatorial Problems and Approximation Solution," with D. K. Friesen Chapter 6 in Current Trends in Programming Methodology, vol III, edited by K. M. Chandy and R. T. Yeh, Prentice Hall, 1978.

"Scheduling with Slack Time," with J. W. S. Liu, and A. L. Liestman, Acta Informatica 17, pp. 31-41, 1982.

"SS/TDMA Time Slot Assignment with Restricted Switching Modes," with J. L. Lewandowski, and J. W. S. Liu, IEEE Transactions on Communications, vol. com-31, pp. 149-154, 1983.

 "Bipartite Folding and Partitioning of a PLA," with J. R. Egan, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 3, pp. 191-199, July, 1984.

"Permutation Channel Routing," with H. W. Leong, Proceedings of the 1985 ICCD Conference, pp. 579-584, October, 1985.

"Multiple PLA Folding by the Method of Simulated Annealing," with D. F. Wong, and H. W. Leong, Proceedings of the 1986 Custom Integrated Circuits Conference, pp. 351-355, May, 1986.

"A New Algorithm for Floorplan Design," with D. F. Wong, Proceedings of the 23rd Design Automation Conference, pp. 101-107, June, 1986.

"PLA Folding by Simulated Annealing," with D. F. Wong, and H. W. Leong, IEEE Journal of Solid-State Circuits, vol. SC-22, no. 2, pp. 208-215, 1987.

* "A Force-Directed Global Router," with N. Hasan, Proc. 1987 Stanford Conference on Advanced Research in VLSI, pp. 135-150, 1987.

"SS/TDMA Satellite Communication with k-Permutation Switching Modes," with J. L. Lewandowski, SIAM Journal on Algebraic and Discrete Methods, vol. 8, no. 4, pp. 519-534, October, 1987.

"Discretionary Channel Routing," with H. W. Leong, IEE Proceedings, vol. 135, pt. G, no. 2, pp. 45-57, April, 1988.

"A New Approach to Three- or Four-Layer Channel Routing," with J. Cong, and D. F. Wong, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 10, pp. 1094-1104, October, 1988.

"A New Approach to the Pin Assignment Problem," with X. Yao, and M. Yamada, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 9, pp. 999-1006, September, 1989.

"On the k-Layer Planar Subset and Via Minimization Problems," with J. Cong, Proceedings of the European Design Automation Conference, pp. 459-463, March, 1990.

"Solution of a Module Orientation and Rotation Problem," with X. Yao, Proceedings of the European Design Automation Conference, pp. 584-588, March, 1990.

"Over-the-Cell Channel Routing," with J. Cong, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 4, pp. 408-418, April, 1990.

"Disjoint Covers in Replicated Heterogeneous Arrays," with P. K. McKinley, N. Hasan, and R. Libeskind-Hadas, SIAM Journal on Discrete Mathematics, vol. 4, no. 2, pp. 281-292, May, 1991.

"Recent Results in Real-Time Scheduling," with J. W. S. Liu, R. Bettati, D. Gillies, C. C. Han, K. J. Lin, and W. K. Shih, Chapter 4 in  Foundations of Real-Time Computing: Scheduling and Resource Management van Tilborg and Koob ed., Kluwer Academic Publishers, pp. 91-128, 1991.

"On the k-Layer Planar Subset and Topological Via Minimization Problems," with J. Cong, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 8, pp. 972-981, August, 1991.

* "Efficient Bi-Level Reconfiguration Algorithms for Fault-Tolerant Arrays," with R. Libeskind-Hadas, N. Shrivastava, and R. G. Melhem, Proceedings of IEEE International Workshop of Defect and Fault Tolerance in VLSI Systems, pp. 42-51, Dallas, Texas, November, 1992.

* "Two Channel Routing Algorithms for Quickly Customized Logic," with S. K. Dong, Y. Sun, and S. Sato, Proceedings of the European Conference on Design Automation, pp. 122-126, Feb. 1993.

"Physical Models and Efficient Algorithms for Over-the-Cell Routing in Standard Cell Design," with J. Cong, and B. Preas, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 5, pp. 723-734, May, 1993.

* "A Performance Driven Hierarchical Partitioning Placement Algorithm," with T. Gao, and K. C. Chen, Proceedings of European Design Automation Conference, pp. 33-38, September, 1993.

* "A New Performance Driven Macro-Cell Placement Algorithm," with T. Tia, Proceedings of European Design Automation Conference, pp. 66-71, September, 1993.

* "Register Allocation for Data Flow Graphs with Conditional Branches and Loops," with C. Park, and T. Kim, Proceedings of European Design Automation Conference, pp. 586-590, September, 1993.

* "Placement and Placement Driven Technology Mapping for FPGA Synthesis," with T. Gao, K. C. Chen, J. Cong, and Y. Ding, Proceedings of ASIC Conference, pp. 91-94. September, 1993.

"Modified Rate-Monotone Algorithm for Scheduling Periodic Jobs with Deferred Deadlines," with W. K. Shih, and J. W. S. Liu, IEEE Transactions on Software Engineering, vol. 19, no. 12, pp. 1171-1179, December, 1993.

* "A Scheduling Algorithm for Conditional Resource Sharing-A Hierarchical Reduction Approach," with T. Kim, N. Yonezawa, and J. W. S. Liu, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4, pp. 425-438, April, 1994.

* "Optimal Reconfiguration Algorithms for Real-Time Fault Tolerant Processor Arrays," with R. Libeskind-Hadas, N. Shrivastava, and R. G. Melhem, IEEE Trans. on Parallel and Distributed Systems, 6(5), pp. 498-510, May, 1995.

"An Integrated Data Path Synthesis Algorithm Based on Network Flow Method," with T. Kim, Proceedings of Custom Integrated Circuits Conference, pp. 615-618, May, 1995.

"Partial Scan with Pre-selected Scan Signals," with P. Pan, Proceedings of 32nd ACM/IEEE Design Automation Conference, pp. 189-194, June, 1995.

"Area Minimization for Floorplans," with P. Pan, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 1, pp. 123-132, 1995.

"Re-engineering of Timing Constrained Placements for Regular Architectures," with A. Mathur, and K. C. Chen, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 485-490, November, 1995.

* "Timing Driven Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs," with A. Mathur, Proceedings of European Design and Test Conference, pp. 165-169, March, 1996.

* "A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs," with S. Raman, and L. G. Jones, Proceedings of European Design and Test Conference, pp. 170-174 March, 1996.

"Minimum Crosstalk Channel Routing," with T. Gao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 464-474, May, 1996.

"Area Minimization for Hierarchical Floorplans," with P. Pan, and W. Shi, Algorithmica, vol. 15, no. 6, pp. 550-571, June, 1996.

"Optimal Clock Period FPGA Technology Mapping for Sequential Circuits," with P. Pan, Proceedings of 33rd ACM/IEEE Design Automation Conference, pp. 720-725, June, 1996.

"Desensitization for Power Reduction in Sequential Circuits," with X. Chen, and P. Pan, Proceedings of 33rd ACM/IEEE Design Automation Conference, pp. 795-800, June, 1996.

"An Integrated Algorithm for Incremental Data Path synthesis," with T. Kim, Journal of VLSI Signal Processing, vol. 12, no. 3, pp. 265-185, June, 1996.

"Low Power Reduction of Finite State Machine - A Decomposition Approach," with S. H. Chow, Y. C. Ho, and T. T. Hwang, ACM Transactions on Design Automation of Electronic Systems, pp. 315-340, vol. 1, no. 3, July, 1996.

"An Algorithm for Synthesis of System-Level Interface Circuits," with Ki-Seok Chung, and Rajesh K. Gupta, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 442-447, November, 1996.

"Routing for Symmetric FPGAs and FPICs," with Y. Sun, T. C. Wang, and C. K. Wong, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 1, pp. 20-31, 1997.

* "Optimal Graph Constraint Reduction for Symbolic Layout Compaction," with P. Pan, and S. K. Dong, Algorithmica, vol. 18, pp. 560-574, 1997.

"Low Power Multiplexer Decomposition," with U. Narayanan, H. W. Leong, and K. S.  Chung, Proceedings of International Symposium on Low Power Electronics and Design, pp. 269-274, August, 1997.

"Optimal Clock Period Clustering for Sequential Circuits with Retiming," with A. K. Karandikar, and P. Pan, Proceedings of International Conference on Computer Design, pp. 122-127, October, 1997.

"Low Power Logic Synthesis for XOR Based Circuits," with Unni Narayanan, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 570-574, November, 1997.

"Local Transformation Techniques for Multi-Level Logic Circuits Utilizing Circuit Symmetries for Power Reduction," with K. S. Chung, Proceedings of International Symposium on Low Power Electronics and Design, pp. 215-220, August, 1998.

"Low Power Logic Synthesis under a General Delay Model," with U. Narayanan, and P. Pan, Proceedings of the International Symposium on Low Power Electronic Design, pp. 209-214, August, 1998.

"Register Allocation – Hierarchical Reduction Approach," with C. Park, and T. Kim, Journal of VLSI Signal Processing, Vol. 19, no. 3, pp. 269-289, August, 1998.

"A Performance driven Layer Assignment and Routing Algorithm for Multiple Interconnect Trees," with P. Saxena, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 124 - 127, November, 1998.

"Architecture Driven Circuit Partitioning," with C. S. Chen, and T. T. Hwang, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 408 - 411, November, 1998.

"Power Invariant Vector Sequence Compaction," with A. Pinar, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 473 - 476, November, 1998.

"Logic Transformation for Low Power Synthesis," with K. Kim, T. T. Hwang, and S. M. Kang, Proceedings of Conference on Design, Automation and Test in Europe, pp. 158-162, March, 1999.

* "An Efficient Data Path Synthesis Algorithm for Behavioral-Level Power Optimization," with C. Park, and T. Kim, Proceedings of International Symposium on Circuits and Systems, pp. I-294 - I-297, May 1999.

"Crosstalk Minimization using Wire Perturbations," with P. Saxena, Proceedings of 36th ACM/IEEE Design Automation Conference, pp. 100 - 103, June 1999.

* "G-vector: A New Model for Glitch Analysis," with K. S. Chung, and T. Kim, Proceedings of 12th IEEE International ASIC/SOC Conference, pp. 159 - 162, September, 1999.

* "An Integrated Approach to Data Path Synthesis for Low Power," with C. Park, and T. Kim, Proceedings of 12th IEEE International ASIC/SOC Conference, pp. 125 - 129, September, 1999.

"Implication Graph based Domino Logic Synthesis," with K. W. Kim, and S. M. Kang, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 111 - 114, November, 1999.

"Optimal Allocation of Carry-Save-Adders in Arithmetic Optimization," with J. Um, and T. Kim, Proceedings of ACM/IEEE International Conf. on Computer-Aided Design, pp. 410 - 413, November, 1999.

"A Postprocessing Algorithm for Crosstalk-Driven Wire Peturbation," with P. Saxena, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 691-702, June, 2000.

"A Fine-Grained Arithmetic Optimization for High-Performance/Low-Power Data Path Synthesis," with J. Um, and T. Kim, Proceedings of 37th ACM/IEEE Design Automation Conference, pp. 98-103, June, 2000.

"Noise-Aware Power Optimization for on-Chip Interconnect," with K. W. Kim, S. O. Jung, U. Narayanan, and S. M. Kang, Proceedings of International Symposium on Low Power Electronics and Design, July, 2000.

* "Power Optimization of Multi-Level Logic Circuits Utilizing Circuit Symmetries," with K. S. Chung, and T. Kim, International Journal of Electronics, Vol. 87, no. 7, pp. 853-864, July, 2000.

* "A Complete Model for Glitch Analysis in Logic Circuit," with K. S. Chung, and T. Kim, Proceedings of IEEE International ASIC/SOC Conference, September, 2000.

* "G-vector: A New Model for Glitch Analysis in Logic Circuits," with K. S. Chung, and T. Kim, Journal of VLSI Signal Processing, Vol. 27, No. 3, pp. 235-252, 2001.

* "A Static Estimation Technique of Power Sensitivity in Logic Circuits," with T. Kim, and K. S. Chung, Proceedings of 38th ACM/IEEE Design Automation Conference, pp.215-219, 2001.

* "Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique," with K. W. Kim, S. O. Jung, and P. Saxena, Proceedings of 38th ACM/IEEE Design Automation Conference, pp.732-737, 2001.

"Domino logic synthesis based on implication graph," with Ki-Wook Kim, Taewhan Kim and Sung-Mo Kang, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 232 - 240, February 2002.

"Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application", with S. L. Lung, D. Lin, S. S. Chen, G. Weng, S. C. Lai, C. W. Tsai, T. B. Wu and R. Liu, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 479 - 482, May 2002.

"A technology mapping algorithm for CPLD architectures," with Shih-Liang Chen and Ting Ting Hwang, Proceedings of IEEE International Conference on Field-Programmable Technology, pp. 204 - 210, December, 2002.

"Noise-aware interconnect power optimization in domino logic synthesis," with Ki-Wook Kim, Seong-Ook Jung, U Narayanan and Sung-Mo Kang, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 79 - 89, February, 2003.


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